Variable capacitance chamber component incorporating a semiconductor junction and methods of manufacturing and using thereof

ABSTRACT

A replaceable chamber element for use in a plasma processing system, such as a plasma etching system, is described. The replaceable chamber element includes a chamber component configured to be exposed to plasma in a plasma processing system, wherein the chamber component is fabricated to include a semiconductor junction, and wherein a capacitance of the chamber component is varied when a voltage is applied across the semiconductor junction.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to co-pending U.S. patent application Ser. No. ______, entitled “VARIABLE CAPACITANCE CHAMBER COMPONENT INCORPORATING FERROELECTRIC MATERIALS AND METHODS OF MANUFACTURING AND USING THEREOF”, Docket No. TEA-076, filed on even date herewith. The entire content of this application is herein incorporated by reference in its entirety.

FIELD OF INVENTION

The invention relates to a replaceable chamber element for use in a plasma processing system, and methods for manufacturing the replaceable chamber element and performing a plasma-assisted process using the replaceable chamber element.

BACKGROUND OF THE INVENTION

The fabrication of integrated circuits (IC) in the semiconductor industry typically employs plasma to create and assist surface chemistry within a vacuum processing system necessary to remove material from and deposit material on a substrate. In general, plasma is formed within the processing system under vacuum conditions by heating electrons to energies sufficient to sustain ionizing collisions with a supplied process gas. Moreover, the heated electrons can have energy sufficient to sustain dissociative collisions and, therefore, a specific set of gases under predetermined conditions (e.g., chamber pressure, gas flow rate, etc.) are chosen to produce a population of charged species and chemically reactive species suitable to the particular process being performed within the system (e.g., etching processes where materials are removed from the substrate or deposition processes where materials are added to the substrate).

Although the formation of a population of charged species (ions, etc.) and chemically reactive species is necessary for performing the function of the plasma processing system (i.e., material etch, material deposition, etc.) at the substrate surface, other chamber component surfaces on the interior of the plasma processing chamber are exposed to the physically and chemically active plasma and, in time, can erode. The erosion of exposed chamber components in the plasma processing system can lead to a gradual degradation of the plasma processing performance and ultimately to complete failure of the system.

As an example, during plasma etching for semiconductor device fabrication, the termination of the peripheral edge of the substrate is important and, when not addressed properly, can change plasma properties and affect etching uniformity. A chamber component, known as a focus ring, is located beyond the peripheral edge of the substrate and, dependent on the material composition of the focus ring, it may spread or confine plasma above the substrate to improve etching performance, such as etching uniformity, especially at the peripheral edge of the substrate. However, the focus ring is consumed during plasma etching, which in turn degrades etching uniformity. And, as a consequence, the focus ring must be replaced about every 200-400 hours the plasma processing system is in operation.

As another example, during plasma etching for semiconductor device fabrication, chamber matching is also a critical concern. The consumption of chamber components (e.g., focus ring, cover ring, electrode plate, etc.), the deposition of polymer on chamber components (e.g., deposition shield, etc.), and chamber capacity change the capacitance of plasma processing chamber, which results in variable plasma properties as well as variable etching uniformity.

SUMMARY OF THE INVENTION

Embodiments of the invention relate to a replaceable chamber element for use in a plasma processing system, and methods for manufacturing the replaceable chamber element and performing a plasma-assisted process using the replaceable chamber element. Embodiments of the invention further relate to a replaceable chamber element having a variable capacitance.

According to one embodiment, a replaceable chamber element for use in a plasma processing system, such as a plasma etching system, is described. The replaceable chamber element includes a chamber component configured to be exposed to plasma in a plasma processing system, wherein the chamber component is fabricated to include a semiconductor junction, and wherein a capacitance of the chamber component is varied when a voltage is applied across the semiconductor junction.

According to another embodiment, a method for manufacturing a replaceable chamber element for use in a plasma processing system is described. The method includes: fabricating a first element composed of a first material, wherein the first material is selected from the group consisting of a p-type semiconductor material, an n-type semiconductor material, or a metal; fabricating a second element composed of a second material, wherein the second material is selected from the group consisting of a p-type semiconductor material, an n-type semiconductor material, a doped semiconductor material, an un-doped semiconductor material, or an oxidized semiconductor material; and fusing the first element to the second element to create a chamber component having a semiconductor junction formed therebetween.

According to yet another embodiment, a method for performing a plasma-assisted process is described. The method includes disposing a chamber component in a plasma processing system, wherein the chamber component is fabricated to include a semiconductor junction. The method further includes forming plasma for performing a plasma-assisted process in the plasma processing system.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A through 1C provide schematic illustrations of a plasma processing system according to several embodiments;

FIG. 2 provides an illustration of a method of varying the capacitance of a replaceable chamber element according to an embodiment;

FIGS. 3A through 3C illustrate a method of varying the capacitance of a replaceable chamber element according to an embodiment;

FIGS. 3D and 3E illustrate a method of varying the capacitance of a replaceable chamber element according to other embodiments;

FIG. 4 provides an illustration of a focus ring and a method of fabricating according to an embodiment;

FIGS. 5A and 5B provide a top view of a focus ring and an exploded cross-sectional view of an implementation of a variable capacitance focus ring in a plasma processing system according to an embodiment;

FIGS. 5C and 5D provide an exploded cross-sectional view of an implementation of a variable capacitance focus ring in a plasma processing system according to other embodiments;

FIGS. 6A and 6B provide an illustration of an electrode plate and a method of fabricating according to various embodiments;

FIG. 7 provides an illustration of a deposition shield and a method of fabricating according to an embodiment;

FIG. 8 provides a flow chart illustrating a method of manufacturing a replaceable chamber element according to another embodiment; and

FIG. 9 provides a flow chart illustrating a method of performing a plasma-assisted process according to yet another embodiment.

DETAILED DESCRIPTION OF SEVERAL EMBODIMENTS

A replaceable chamber element for use in a plasma processing system is disclosed in various embodiments. However, one skilled in the relevant art will recognize that the various embodiments may be practiced without one or more of the specific details, or with other replacement and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention.

Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the invention. Nevertheless, the invention may be practiced without specific details. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

Reference throughout this specification to “one embodiment” or “an embodiment” or variation thereof means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention, but do not denote that they are present in every embodiment. Thus, the appearances of the phrases such as “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

Nonetheless, it should be appreciated that, contained within the description are features which, notwithstanding the inventive nature of the general concepts being explained, are also of an inventive nature.

“Substrate” as used herein generically refers to the object being processed in accordance with embodiments of the invention. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer or a layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not intended to be limited to any particular base structure, underlying layer or overlying layer, patterned or unpatterned, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures. The description below may reference particular types of substrates, but this is for illustrative purposes only and not limitation.

As described above, plasma processing systems and, in particular, plasma etching systems, contain one or more replaceable chamber elements exposed to plasma that require periodic replacement or refurbishment due to plasma erosion and consumption. For example, the one or more replaceable chamber elements may include a focus ring, a shield ring, a deposition shield (or chamber liner), a baffle plate, a bellows shield, an electrode plate, or an antenna window. According to various embodiments, a replaceable chamber element having a variable capacitance is described that, among other things, may be utilized to adjust one or more plasma properties, such as plasma density, to achieve any one of the following: (i) alter plasma uniformity and etching uniformity; (ii) improve plasma processing chamber matching; (iii) reduce the seasoning time following the cleaning of the plasma processing chamber; (iv) increase lifetime of the replaceable chamber element by compensating for plasma erosion and consumption; and (v) improve substrate-to-substrate and lot-to-lot matching.

Therefore, according to an embodiment, a plasma processing system 100A configured to perform a plasma-assisted process on a substrate 135 is depicted in FIG. 1A. The plasma processing system 100A comprises a plasma processing chamber 110, an upper assembly 120A, an electrode plate/antenna assembly 124A, a substrate holder 130 for supporting substrate 135, a pumping duct 140 coupled to a vacuum pump (not shown) for providing a reduced pressure atmosphere in plasma processing chamber 110, and one or more replaceable chamber elements (160, 162, 164, 126A, 114) having a variable capacitance.

Plasma processing chamber 110 can facilitate the formation of plasma in a process space 112 adjacent substrate 135. Plasma can be utilized to create materials specific to a pre-determined materials process, and/or to aid the removal of material from the exposed surfaces of substrate 135. The plasma processing system 100A may be configured to process substrates of any size, such as 200 mm substrates, 300 mm substrates, 450 mm substrates, or larger. For example, the plasma processing system 100 may comprise a plasma etching system.

In the illustrated embodiment of FIG. 1A, upper assembly 120A may provide a grounded electrode opposite substrate 135. The upper assembly 120A comprises electrode plate/antenna assembly 124A that includes an electrode plate 126A and an electrode 128A. Electrode 128A may be electrically coupled to ground, as shown, and electrode plate 126A may be composed of a material compatible with plasma in process space 112. Due to the erosive nature of plasma, electrode plate 126A may be consumed and may require periodic replacement or refurbishment. For example, electrode plate 126A may be a replaceable element composed of a semiconductor, a conductor, or an insulator, or a combination of two or more thereof. The semiconductor material may, for example, include silicon (Si), silicon carbide (SiC_(x)), or silicon-germanium (SiGe_(y)), that may be removably fastened to electrode 128A.

Alternatively, in the illustrated embodiment of FIG. 1 B, an upper assembly 120B of a plasma processing system 100B is shown. Upper assembly 120B may provide a powered RF electrode opposite substrate 135 for plasma production. The upper assembly 120B comprises an electrode plate/antenna assembly 124B that includes an electrode plate 126B and an electrode 128B. Electrode 128B may be electrically coupled to a source of radio frequency (RF) energy, such as an RF generator, as shown, and electrode plate 126B may be composed of a material compatible with plasma in process space 112. Due to the erosive nature of plasma, electrode plate 126B may be consumed and may require periodic replacement or refurbishment. For example, electrode plate 126B may be a replaceable element composed of a semiconductor, a conductor, or an insulator, or a combination of two or more thereof. The semiconductor material may, for example, include silicon (Si), silicon carbide (SiC_(x)), or silicon-germanium (SiGe_(y)), that may be removably fastened to electrode 128B.

As shown in FIGS. 1A and 1B, the plasma processing system (100A, 100B) may be configured as a capacitively coupled plasma (CCP) system. Alternatively, the plasma processing system (100A, 100B) may be configured as an inductively coupled plasma (ICP) system.

Alternatively yet, in the illustrated embodiment of FIG. 1C, an upper assembly 120C of a plasma processing system 100C is shown. Upper assembly 120C may provide a powered microwave antenna opposite substrate 135 for plasma production. The upper assembly 120C comprises an electrode plate/antenna assembly 124C that includes an antenna window 126C and an antenna 128C. Antenna 128C may be electrically coupled to a source of radio frequency (RF) energy, such as a microwave generator, as shown, and antenna window 126C may be composed of a material compatible with plasma in process space 112. Due to the erosive nature of plasma, antenna window 126C may be consumed and may require periodic replacement or refurbishment. For example, antenna window 126C may be a replaceable element composed of a semiconductor, a conductor, or an insulator, or a combination of two or more thereof. The semiconductor material may, for example, include silicon (Si), silicon carbide (SiC_(x)), or silicon-germanium (SiGe_(y)), that may be removably fastened to antenna 128C.

As shown in FIG. 1C, the plasma processing system 100C may be configured as a surface wave plasma (SWP) system. Upper assembly 120C may include a slotted plane antenna (SPA), such as a radial line slot antenna (RLSA).

Although not shown in FIGS. 1A through 1C, a direct current (DC) power supply may be coupled to the upper assembly (120A, 1208, 120C) opposing substrate 135. The DC power supply may include a variable DC power supply. Additionally, the DC power supply may include a bipolar DC power supply. The DC power supply may further include a system configured to perform at least one of monitoring, adjusting, or controlling the polarity, current, voltage, or on/off state of the DC power supply. Once plasma is formed, the DC power supply may facilitate the formation of an electron beam. An electrical filter (not shown) may be utilized to de-couple RF power from the DC power supply.

For example, the DC voltage applied to upper assembly (120A, 120B, 120C) by the DC power supply may range from approximately −2000 volts (V) to approximately 1000 V. Desirably, the absolute value of the DC voltage has a value equal to or greater than approximately 100 V, and more desirably, the absolute value of the DC voltage has a value equal to or greater than approximately 500 V. Additionally, it is desirable that the DC voltage has a negative polarity. Furthermore, it is desirable that the DC voltage is a negative voltage having an absolute value greater than the self-bias voltage generated on a surface of the upper assembly (120A, 1208, 120C).

Referring to FIGS. 1A through 1C, the plasma processing chamber 110 may include a chamber liner or deposition shield 114 configured to be coupled to at least a portion of an interior surface of the plasma processing chamber 110. Due to the erosive nature of plasma, deposition shield 114 may be consumed and may require periodic replacement or refurbishment. The inventors suspect that the deposition of polymer on the deposition shield 114 during etching will have less influence on the etching uniformity and chamber matching when capacitance adjustment is utilized. As a result, the frequency for system maintenance, including wet clean, will be decreased. For example, deposition shield 114 may be a replaceable element composed of a semiconductor, a conductor, or an insulator, or a combination of two or more thereof. The semiconductor material may, for example, include silicon (Si), silicon carbide (SiC_(x)), or silicon-germanium (SiGe_(y)), that may be removably fastened to plasma processing chamber 110.

Referring to FIGS. 1A through 1C, substrate holder 130 further comprises a focus ring 160, and may optionally comprise a shield ring 160 and a bellows shield 154. Due to the erosive nature of plasma, focus ring 160 may be consumed and may require periodic replacement or refurbishment. For example, focus ring 160 may be a replaceable element composed of a semiconductor, a conductor, or an insulator, or a combination of two or more thereof. The semiconductor material may, for example, include silicon (Si), silicon carbide (SiC_(x)), or silicon-germanium (SiGe_(y)), that may be removably fastened to substrate holder 130.

Additionally, substrate 135 can be affixed to the substrate holder 130 via a clamping system (not shown), such as a mechanical clamping system or an electrical clamping system (e.g., an electrostatic clamping system). Furthermore, substrate holder 130 can include a heating system (not shown) or a cooling system (not shown) that is configured to adjust and/or control the temperature of substrate holder 130 and substrate 135. The heating system or cooling system may comprise a re-circulating flow of heat transfer fluid that receives heat from substrate holder 130 and transfers heat to a heat exchanger system (not shown) when cooling, or transfers heat from the heat exchanger system to substrate holder 130 when heating. In other embodiments, heating/cooling elements, such as resistive heating elements, or thermo-electric heaters/coolers can be included in the substrate holder 130, as well as the chamber wall of the plasma processing chamber 110 and any other component within the plasma processing system (100A, 1008, 100C).

Furthermore, a heat transfer gas can be delivered to the backside of substrate 135 via a backside gas supply system 136 in order to improve the gas-gap thermal conductance between substrate 135 and substrate holder 130. Such a system can be utilized when temperature control of the substrate is required at elevated or reduced temperatures. For example, the backside gas supply system can comprise a two-zone gas distribution system, wherein the helium gas-gap pressure can be independently varied between the center and the edge of substrate 135.

In the embodiments shown in FIGS. 1A through 1C, substrate holder 130 can comprise a substrate holder electrode (not shown) through which RF power is optionally coupled to the processing plasma in process space 112. For example, substrate holder 130 can be electrically biased at a RF voltage via the transmission of RF power from a RF generator (not shown) through an optional impedance match network to substrate holder 130. The RF electrical bias can serve to heat electrons to form and maintain plasma. In this configuration, the system can operate as a reactive ion etch (RIE) reactor, wherein the chamber and an upper gas injection electrode serve as ground surfaces. A typical frequency for the RF bias can range from about 0.1 MHz to about 100 MHz. RF systems for plasma processing are well known to those skilled in the art.

Furthermore, the electrical bias of the substrate holder electrode at a RF voltage may be pulsed using pulsed bias signal controller (not shown). The RF power output from the RF generator may be pulsed between an off-state and an on-state, for example.

Alternately, RF power is applied to the substrate holder electrode at multiple frequencies. Furthermore, impedance match network can improve the transfer of RF power to plasma in plasma processing chamber 110 by reducing the reflected power. Match network topologies (e.g. L-type, π-type, T-type, etc.) and automatic control methods are well known to those skilled in the art.

The upper assembly (120A, 120B, 120C) may include a gas distribution system (not shown). The gas distribution system may comprise a showerhead design for introducing a mixture of process gases. Alternatively, gas distribution system may comprise a multi-zone showerhead design for introducing a mixture of process gases and adjusting the distribution of the mixture of process gases above substrate 135. For example, the multi-zone showerhead design may be configured to adjust the process gas flow or composition to a substantially peripheral region above substrate 135 relative to the amount of process gas flow or composition to a substantially central region above substrate 135. The gas distribution system may be integrated with the electrode plate (126A, 126B) or antenna window 126C, for example.

A vacuum pumping system may be coupled to pumping duct 140. For example, the vacuum pumping system may include a turbo-molecular vacuum pump (TMP) capable of a pumping speed up to about 5000 liters per second (and greater) and a gate valve for throttling the chamber pressure. In conventional plasma processing devices utilized for dry plasma etching, a 1000 to 3000 liter per second TMP can be employed. TMPs are useful for low pressure processing, typically less than about 50 mTorr. For high pressure processing (i.e., greater than about 100 mTorr), a mechanical booster pump and dry roughing pump can be used. Furthermore, a device for monitoring chamber pressure (not shown) can be coupled to the plasma processing chamber 110.

The plasma processing chamber 110 may include a baffle plate 164 configured to be coupled to an entrance to the pumping duct 140 or an annular region surrounding a peripheral edge of substrate holder 130 in plasma processing chamber 110. Due to the erosive nature of plasma, baffle plate 164 may be consumed and may require periodic replacement or refurbishment. For example, baffle plate 164 may be a replaceable element composed of a semiconductor, a conductor, or an insulator, or a combination of two or more thereof. The semiconductor material may, for example, include silicon (Si), silicon carbide (SiC_(x)), or silicon-germanium (SiGe_(y)), that may be removably fastened to substrate holder 130 or plasma processing chamber 110.

Any one of the replaceable chamber elements, such as focus ring 160, shield ring 162, electrode plate (126A, 126B), antenna window 126C, deposition shield 114, baffle plate 164, bellows shield 154, etc., may include a coating applied to at least a portion of an exposed surface. The coating may be composed of silicon, quartz, silicon carbide, silicon nitride, carbon, alumina, sapphire, ceramic, fluoropolymer, or polyimide. Additionally, the coating may include a spray coating. The coating may include at least one of a Group III element (Group III refers to the classical or old IUPAC notation in the Periodic Table of Elements; according to the revised or new IUPAC notation, this Group would refer to Group 13) and a Lanthanon element, for example. The coating may comprise at least one of Al₂O₃, Yttria (Y₂O₃), Sc₂O₃, Sc₂F₃, YF₃, La₂O₃, CeO₂, Eu₂O₃, and Dy₂O₃. Methods of applying spray coatings are well known to those skilled in the art of surface material treatment.

As described above with reference to FIGS. 1A through 10, plasma processing system (100A, 1008, 1000) may include one or more replaceable chamber elements, such as focus ring 160, shield ring 162, electrode plate (126A, 126B), antenna window 1260, deposition shield 114, baffle plate 164, bellows shield 154, etc. At least one replaceable chamber element possesses a variable capacitance. The variable capacitance replaceable chamber element is designed to include a semiconductor junction. Therein, when a bias voltage is applied across the semiconductor junction, the capacitance is varied. The semiconductor junction may include a p-n junction, a metal-semiconductor junction, or a metal-oxide-semiconductor junction.

As shown in FIG. 2, a replaceable chamber element for use in a plasma processing system is illustrated. The replaceable chamber element includes a chamber component 200 configured to be exposed to plasma in a plasma processing system, wherein the chamber component 200 includes a semiconductor junction 210 disposed between a first electrode 201 and a second electrode 202. The capacitance of semiconductor junction 210 may be expressed as C=εA/d, wherein ε is the (effective) dielectric constant of the semiconductor junction 210, d is the (effective) thickness of the semiconductor junction, and A is the (effective) area of the semiconductor junction 210. To vary the capacitance C, the dielectric constant ε, the thickness d, or the area A, or any combination thereof may be adjusted.

In one embodiment, as illustrated in FIG. 3A, the replaceable chamber element includes a chamber component 300A configured to be exposed to plasma in a plasma processing system, wherein the chamber component 300A includes a first region 301 composed of a p-type semiconductor material, a second region 302 composed of an n-type semiconductor material, and a third region 303 that represents a p-n junction formed therebetween. The p-type and n-type portions of the first and second regions (301, 302), respectively, are relatively conductive. The third region 303, formed between the (p-type and n-type) first and second regions (301, 302), becomes depleted of charge carriers, and hence is less conductive. The third region 303, which may be characterized as a depletion layer having a first depletion layer thickness 305, may behave as a capacitor having a capacitance C=εA/d, wherein ε is the dielectric constant of the depletion layer, d is the depletion layer thickness, and A is the area. Without an added bias voltage, the depletion layer thickness (d) remains substantially fixed.

When a first bias voltage (forward bias) is applied across the p-n junction, the first depletion layer thickness 305 is decreased to a second depletion layer thickness 306 (see FIG. 3B). When the polarity is reversed and a second bias voltage (reverse bias) is applied across the p-n junction, the first depletion layer thickness 305 is increased to a third depletion layer thickness 307 (see FIG. 3C). The reverse bias capacitance is given by the following expression:

C_(j)˜(V_(bi)+V_(R))^(−n),

wherein W_(bi) represents the built-in voltage of the p-n junction (function of band-gap and doping level), V_(R) represents the reverse bias voltage, and n is an exponent (having a value of about ⅓ for a linearly graded p-n junction, a value of about ½ for an abrupt p-n junction, and a value of 2 for a hyper-abrupt p-n junction).

As one example, the chamber component 300A may be formed by implanting an n-type dopant into an element composed of a p-type semiconductor material to change the composition of at least a portion of the element from a p-type semiconductor material to an n-type semiconductor material and, thus, create a p-n junction at the interface formed therebetween. As another example, the chamber component 300A may be formed by implanting a p-type dopant into an element composed of an n-type semiconductor material to change the composition of at least a portion of the element from an n-type semiconductor material to a p-type semiconductor material and, thus, create a p-n junction at the interface formed therebetween. As yet another example, the chamber component 300A may be formed by bonding a first element composed of a p-type semiconductor material to a second element composed of an n-type semiconductor material, wherein a p-n junction is formed therebetween. The chamber component having a p-n junction may be fabricated using any combination of growing, oxidizing, depositing, doping, machining, polishing, bonding, or fusing techniques. The initial depletion layer thickness may vary depending upon the technique used to fabricate the p-n junction.

In another embodiment, as illustrated in FIG. 3D, the replaceable chamber element includes a chamber component 300B configured to be exposed to plasma in a plasma processing system, wherein the chamber component 300B includes a first region 311 composed of a metal, a second region 312 composed of semiconductor material, and a third region 313 that represents a metal-semiconductor junction formed therebetween.

The semiconductor material may include a p-type semiconductor material or an n-type semiconductor material. The metal and semiconductor (e.g., p-type or n-type) portions of the first and second regions (311, 312), respectively, are relatively conductive. The third region 313, formed between the first and second regions (311, 312), becomes depleted of charge carriers, and hence is less conductive. The third region 313, which may be characterized as a depletion layer having a first depletion layer thickness 315, may behave as a capacitor having a capacitance C=εA/d, wherein ε is the dielectric constant of the depletion layer, d is the depletion layer thickness, and A is the area. Without an added bias voltage, the depletion layer thickness (d) remains substantially fixed. When a bias voltage is applied across the metal-semiconductor junction, the first depletion layer thickness 315 is increased or decreased to a new depletion layer thickness. As a result, the capacitance of the metal-semiconductor junction is varied.

As one example, the chamber component 300B may be formed by depositing a metal layer on an element composed of a p-type or n-type semiconductor material, thus, creating a metal-semiconductor junction at the interface formed therebetween. As another example, the chamber component 300B may be formed by bonding a first element composed of a metal to a second element composed of an n-type or p-type semiconductor material, wherein a metal-semiconductor junction is formed therebetween. As yet another example, the chamber component 300B may be formed by bonding a first element composed of a metal to a second element composed of an n-type or p-type semiconductor material having a metal layer deposited thereon, wherein a metal-semiconductor junction is formed therebetween. The chamber component having a metal-semiconductor junction may be fabricated using any combination of growing, oxidizing, depositing, doping, machining, polishing, bonding, or fusing techniques. The initial depletion layer thickness may vary depending upon the technique used to fabricate the metal-semiconductor junction.

In yet another embodiment, as illustrated in FIG. 3E, the replaceable chamber element includes a chamber component 300C configured to be exposed to plasma in a plasma processing system, wherein the chamber component 300C includes a first region 321 composed of a metal, a second region 322 composed of semiconductor material, and a third region 323 composed of an insulator to form a metal-oxide-semiconductor junction.

The semiconductor material may include a p-type semiconductor material or an n-type semiconductor material. The metal and semiconductor (e.g., p-type or n-type) portions of the first and second regions (321, 322), respectively, are relatively conductive. The third region 323, formed between the first and second regions (321, 322), is an oxide, and hence is less conductive. When a bias voltage is applied across the metal-oxide-semiconductor junction, the capacitance of the metal-oxide-semiconductor junction is varied.

As one example, the chamber component 300C may be formed by depositing a metal layer and an oxide layer on an element composed of a p-type or n-type semiconductor material, thus, creating a metal-oxide-semiconductor junction at the interface formed therebetween. As another example, the chamber component 300C may be formed by bonding a first element composed of a metal to a second element composed of an oxidized n-type or p-type semiconductor material, wherein a metal-oxide-semiconductor junction is formed therebetween. As yet another example, the chamber component 300C may be formed by bonding a first element composed of a metal to a second element composed of an oxidized n-type or p-type semiconductor material having a metal layer deposited thereon, wherein a metal-oxide-semiconductor junction is formed therebetween. The chamber component having a metal-oxide-semiconductor junction may be fabricated using any combination of growing, oxidizing, depositing, doping, machining, polishing, bonding, or fusing techniques. The initial depletion layer thickness may vary depending upon the technique used to fabricate the metal-semiconductor junction.

Referring now to FIG. 4, a focus ring 400 and a method of fabricating thereof are illustrated according to an embodiment. The focus ring 400 originates from a first ring 401 composed of a p-type semiconductor material, and a second ring 402 composed of an n-type semiconductor material, wherein a first contact surface 403 on the first ring 401 is contacted with and bonded to a second contact surface 404 on the second ring 402 to form a p-n junction at interface 405. Alternatively, the first ring 401 is composed of an n-type semiconductor material and the second ring 402 is composed of a p-type semiconductor material.

The first ring 401 and the second ring 402 may contain Si, C, or Ge, or any combination thereof. For example, the first ring 401 may be composed of p-type Si, and the second ring 402 may be composed of n-type Si. Alternatively, for example, the first ring 401 may be composed of n-type Si, and the second ring 402 may be composed of p-type Si.

The first ring 401 and the second ring 402 may further include a dopant. The dopant for forming a p-type semiconductor material may include a Group III element (Group III refers to the classical or old IUPAC notation in the Periodic Table of Elements; according to the revised or new IUPAC notation, this Group would refer to Group 13), such as boron (B). The dopant for forming an n-type semiconductor material may include a Group V element (Group V refers to the classical or old IUPAC notation in the Periodic Table of Elements; according to the revised or new IUPAC notation, this Group would refer to Group 15), such as phosphorus (P) or arsenic (As).

The first ring 401 may be bonded to the second ring 402 using a fusion process, such as a silicon fusion process. The fusion process will be described in greater detail below.

Referring now to FIGS. 5A and 5B, a top view of a focus ring and an exploded cross-sectional view of an implementation of a variable capacitance focus ring in a plasma processing system are depicted according to an embodiment. As shown in FIG. 5A, a focus ring 500A includes an inner radial edge 511 and an outer radial edge 512. Focus ring 500A further includes an optional step 515 located at the inner radial edge 511, wherein step 515 is configured to underlie the peripheral edge of a substrate 525.

FIG. 5B provides an exploded cross-sectional view of substrate holder 520 including section A-A of focus ring 500A. Substrate holder 520 may include electrostatic clamp (ESC) layer 522 that includes an ESC electrode for electrically clamping substrate 525 to substrate holder 520. Additionally, substrate holder 520 may include edge insulator 530 through which electrical connection to focus ring 500A may be included.

Focus ring 500A includes a first portion 501A composed of a p-type semiconductor material and a second portion 502A composed of an n-type semiconductor material to form a p-n junction 510A therebetween. Additionally, the first portion 501A includes a first surface 503A configured to be coupled to a first contact electrode 551 at a first voltage, and the second portion 502A includes a second surface 504A configured to be coupled to a second contact electrode 552 at a second voltage. Furthermore, substrate holder 520 includes a voltage source 540 having a first terminal coupled to the first contact electrode 551 and a second terminal coupled to the second contact electrode 552, wherein a voltage difference between the first terminal and the second terminal is used to vary the capacitance of the focus ring 500A.

The voltage source 540 may include a direct current (DC) or alternating current (AC) voltage source. The voltage source 540 may include a variable DC power supply, and may include a bipolar DC power supply. The voltage source 540 may further include a filter 545 configured to protect the voltage source 540 from RF power relating to plasma formation.

According to another embodiment, as shown in FIG. 5C, focus ring 500B includes a first portion 501 B composed of a metal and a second portion 502B composed of a p-type or an n-type semiconductor material to form a metal-semiconductor junction 510B therebetween. Additionally, the first portion 501 B includes a first surface 503B configured to be coupled to a first contact electrode 551 at a first voltage, and the second portion 502B includes a second surface 504B configured to be coupled to a second contact electrode 552 at a second voltage. Furthermore, substrate holder 520 includes a voltage source 540 having a first terminal coupled to the first contact electrode 551 and a second terminal coupled to the second contact electrode 552, wherein a voltage difference between the first terminal and the second terminal is used to vary the capacitance of the focus ring 500B.

According to yet another embodiment, as shown in FIG. 5D, focus ring 500C includes a first portion 501C composed of a metal, a second portion 502C composed of a p-type or an n-type semiconductor material, and a third portion 510C composed of an insulator disposed therebetween to form a metal-oxide-semiconductor junction. Additionally, the first portion 501C includes a first surface 503C configured to be coupled to a first contact electrode 551 at a first voltage, and the second portion 502C includes a second surface 504C configured to be coupled to a second contact electrode 552 at a second voltage. Furthermore, substrate holder 520 includes a voltage source 540 having a first terminal coupled to the first contact electrode 551 and a second terminal coupled to the second contact electrode 552, wherein a voltage difference between the first terminal and the second terminal is used to vary the capacitance of the focus ring 500C.

Referring now to FIG. 6A, an electrode plate 600 and a method of fabricating thereof are illustrated according to an embodiment. While this embodiment is described in the context of an electrode plate, it may also be applicable to an antenna window or a baffle plate. The electrode plate 600 originates from a first plate 601 composed of a p-type semiconductor material, and a second plate 602 composed of an n-type semiconductor material, wherein a first contact surface 603 on the first plate 601 is contacted with and bonded to a second contact surface 604 on the second plate 602 to form a p-n junction at interface 605. Alternatively, the first plate 601 is composed of an n-type semiconductor material and the second plate 602 is composed of a p-type semiconductor material.

The first plate 601 and the second plate 602 may contain Si, C, or Ge, or any combination thereof. For example, the first plate 601 may be composed of p-type Si, and the second plate 602 may be composed of n-type Si. Alternatively, for example, the first plate 601 may be composed of n-type Si, and the second plate 602 may be composed of p-type Si.

The first plate 601 and the second plate 602 may further include a dopant. The dopant for forming a p-type semiconductor material may include a Group III element (Group III refers to the classical or old IUPAC notation in the Periodic Table of Elements; according to the revised or new IUPAC notation, this Group would refer to Group 13), such as boron (B). The dopant for forming an n-type semiconductor material may include a Group V element (Group V refers to the classical or old IUPAC notation in the Periodic Table of Elements; according to the revised or new IUPAC notation, this Group would refer to Group 15), such as phosphorus (P) or arsenic (As).

The first plate 601 may be bonded to the second plate 602 using a fusion process, such as a silicon fusion process. The fusion process will be described in greater detail below.

As shown in FIG. 6B, an electrode plate 610 may be formed having a graded dopant concentration. The electrode plate 610 may originate from a first plate 611 and a second plate 612, wherein at least one plate includes a first region 613 having a first dopant concentration and a second region 614 having a second dopant concentration. As a result, a p-n junction at interface 615 may possess a variable depletion layer thickness across the electrode plate 610.

Dopant concentration grading may also be employed in other replaceable chamber elements, such as a focus ring, a shield ring, a deposition shield, baffle plate, etc.

Referring now to FIG. 7, a deposition shield 700 and a method of fabricating thereof are illustrated according to an embodiment. The deposition shield 700 originates from a first cylinder portion 701 composed of a p-type semiconductor material, and a second cylinder portion 702 composed of an n-type semiconductor material, wherein a first contact surface 703 on the first cylinder portion 701 is contacted with and bonded to a second contact surface 704 on the second cylinder portion 702 to form a p-n junction at interface 705. Alternatively, the first cylinder portion 701 is composed of an n-type semiconductor material and the second cylinder portion 702 is composed of a p-type semiconductor material.

The first cylinder portion 701 and the second cylinder portion 702 may contain Si, C, or Ge, or any combination thereof. For example, the first cylinder portion 701 may be composed of p-type Si, and the second cylinder portion 702 may be composed of n-type Si. Alternatively, for example, the first cylinder portion 701 may be composed of n-type Si, and the second cylinder portion 702 may be composed of p-type Si.

The first cylinder portion 701 and the second cylinder portion 702 may further include a dopant. The dopant for forming a p-type semiconductor material may include a Group III element (Group III refers to the classical or old IUPAC notation in the Periodic Table of Elements; according to the revised or new IUPAC notation, this Group would refer to Group 13), such as boron (B). The dopant for forming an n-type semiconductor material may include a Group V element (Group V refers to the classical or old IUPAC notation in the Periodic Table of Elements; according to the revised or new IUPAC notation, this Group would refer to Group 15), such as phosphorus (P) or arsenic (As).

The first cylinder portion 701 may be bonded to the second cylinder portion 702 using a fusion process, such as a silicon fusion process. The fusion process will be described in greater detail below.

Referring now to FIG. 8, a method for manufacturing a replaceable chamber element for use in a plasma processing system is described according to another embodiment. The method includes flow chart 800 beginning in 810 with fabricating a first element composed of a p-type semiconductor material. As described above, once the first element is prepared, it may be doped with a p-type dopant.

In 820, a second element composed of an n-type semiconductor material is fabricated. Once the second element is prepared, it may be doped with an n-type dopant.

In 830, the first element is bonded to the second element to create a chamber component having a p-n junction formed there between. The bonding of the first and second elements may include a fusion process, such as a silicon fusion process.

The fusion process may include: (a) pre-treating a first contact surface on the first element and a second contact surface on the second element using a hydrophobic treatment process or a hydrophilic treatment process; and (b) bonding the first contact surface with the second contact surface at a treatment temperature equal to room temperature or greater. The bonding of the first contact surface with the second contact surface at the treatment temperature may include annealing at an elevated treatment temperature to increase a bond strength between the first element and the second element, wherein the elevated treatment temperature may range up to 1000 degrees C. As an example, the elevated treatment temperature may exceed 300 degrees C., or 400 degrees C., or even 500 degrees C.

The hydrophobic treatment process may comprise immersing the first element and the second element in an HF solution to terminate the first contact surface and the second contact surface with H. The hydrophilic treatment process may include treating the first contact surface and the second contact surface with plasma containing O₂, H₂, or NH₃, or any combination of two or more thereof. Alternatively, the hydrophilic treatment process may include immersing the first element and the second element in an RCA solution. Alternatively yet, the hydrophilic treatment process may include combinations thereof.

Referring now to FIG. 9, a method for performing a plasma-assisted process in a plasma processing system is described according to another embodiment. The method includes flow chart 900 beginning in 910 with disposing a chamber component in a plasma processing system, wherein the chamber component is fabricated to include a semiconductor junction.

In 920, a first electrode formed in the chamber component is contacted to a first contact electrode in the plasma processing system.

In 930, a second electrode formed in the chamber component is contacted to a second contact electrode in the plasma processing system.

The method may additionally include, in 940, applying a first voltage to the first contact electrode and a second voltage to the second contact electrode in order to apply a voltage difference across the semiconductor junction. The method may further include, in 950, varying a voltage difference between the first contact electrode and the second contact electrode to vary a capacitance of the chamber component. For example, a capacitance of the chamber component may be varied to increase a lifetime of the chamber component, improve matching between a first plasma processing chamber and a second plasma processing chamber, compensate for a drift in the plasma-assisted process from one substrate to another substrate, or reduce the seasoning time following the cleaning of the plasma processing system, or any combination of two or more thereof.

When a voltage difference is applied across the semiconductor junction (e.g., a p-n junction, a metal-semiconductor junction, or a metal-oxide-semiconductor junction) of the chamber component (e.g., focus ring, shield ring, chamber liner, baffle plate, bellows shield, electrode plate, or antenna window), the capacitance of the chamber component may be varied. By adjusting the capacitance of the chamber component, at least one property of the plasma (e.g., RF current proximate the substrate) may be controlled continuously or non-continuously, which permits achieving a desirable plasma profile (or etch profile, deposition profile, etc.). The ability to vary the capacitance of a chamber component allows for adjustment of plasma properties, including plasma uniformity (or etch uniformity).

While Si-containing semiconductor materials are described above, other semiconductor compounds are also contemplated. The semiconductor material may include a compound semiconductor, such as a III-V compound (e.g., GaAs, GaN, GaP, InAs, InN, InP, etc.), a II-V compound (e.g., Cd₃P₂, etc.), or a II-VI compound (e.g., ZnO, ZnSe, ZnS, etc.) (Groups II, III, V, VI refer to the classical or old IUPAC notation in the Periodic Table of Elements; according to the revised or new IUPAC notation, these Groups would refer to Groups 2, 13, 15, 16, respectively).

Although only certain embodiments of this invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention. 

1. A replaceable chamber element for use in a plasma processing system, comprising: a chamber component configured to be exposed to plasma in a plasma processing system, wherein said chamber component is fabricated to include a semiconductor junction, and wherein a capacitance of said chamber component is varied when a voltage is applied across said semiconductor junction.
 2. The replaceable chamber element of claim 1, wherein said semiconductor junction includes a junction selected from the group consisting of a p-n junction, a metal-semiconductor junction, and a metal-oxide-semiconductor junction.
 3. The replaceable chamber element of claim 1, wherein said chamber component comprises a focus ring, a shield ring, a chamber liner, a baffle plate, an electrode plate, or an antenna window.
 4. The replaceable chamber element of claim 1, wherein said chamber component comprises: a first element composed of a p-type semiconductor material, and a second element composed of an n-type semiconductor material, wherein said second element is bonded to said first element to form a p-n junction.
 5. The replaceable chamber element of claim 4, wherein said chamber component comprises a focus ring, and wherein said first element is a first ring composed of p-type silicon (Si) and said second element is a second ring composed of n-type silicon (Si).
 6. The replaceable chamber element of claim 4, wherein said first element, or said second element, or both said first element and said second element contain Si, C or Ge, or any combination of two or more thereof.
 7. The replaceable chamber element of claim 4, wherein said first element, or said second element, or both said first element and said second element further contain a dopant.
 8. The replaceable chamber element of claim 4, wherein said second element is bonded to said first element using a silicon fusion process.
 9. The replaceable chamber element of claim 4, wherein said first element includes a first surface configured to be coupled to a first contact electrode at a first voltage, and wherein said second element includes a second surface configured to be coupled to a second contact electrode at a second voltage of opposing polarity to said first voltage.
 10. The replaceable chamber element of claim further comprising: a voltage source having a first terminal coupled to a first contact electrode on said chamber component and a second terminal coupled to a second contact electrode on said chamber component, wherein a voltage polarity and/or a voltage difference between said first terminal and said second terminal is used to change said capacitance of said chamber component.
 11. A method for manufacturing a replaceable chamber element for use n plasma processing system, comprising: fabricating a first element composed of a first material, said first material selected from the group consisting of a p-type semiconductor material, an n-type semiconductor material, or a metal; fabricating a second element composed of a second material, said second material selected from the group consisting of a p-type semiconductor material, an n-type semiconductor material, a doped semiconductor material, an un-doped semiconductor material, or an oxidized semiconductor material; and fusing said first element to said second element to create a chamber component having a semiconductor junction formed therebetween.
 12. The method of claim 11, further comprising: grading a concentration of a p-type dopant in said first element; or grading a concentration of an n-type dopant in said second element; or grading a concentration of a p-type dopant in said first element and grading a concentration of an n-type dopant in said second element.
 13. The method of claim 11, wherein said fusing said first element to said second element comprises: pre-treating a first contact surface on said first element and a second contact surface on said second element using a hydrophobic treatment process or a hydrophilic treatment process, and bonding said first contact surface with said second contact surface at a treatment temperature equal to room temperature or greater.
 14. The method of claim 11, further comprising: forming a protective layer on an exterior surface of said chamber component, in said protective layer is arranged to be exposed to plasma.
 15. A method for performing a plasma-assisted process, comprising: disposing a chamber component in a plasma processing system, said chamber component being fabricated to include a semiconductor junction; and forming plasma for performing a plasma-assisted process in said plasma processing system.
 16. The method of claim 15, wherein said semiconductor junction includes a junction selected from the group consisting of a p-n junction, a metal-semiconductor junction, and a metal-oxide-semiconductor junction.
 17. The method of claim 15, further comprising: varying a capacitance of said chamber component to adjust at least one property of said plasma in said plasma processing system, said at least one property including a plasma uniformity or an etch uniformity.
 18. The method of claim 15, further comprising: coupling a first electrode formed on said chamber component to a first contact electrode in said plasma processing system; coupling a second electrode formed on said chamber component to a second contact electrode in said plasma processing system; and applying a voltage difference across said semiconductor junction between said first electrode and said second electrode by coupling a first voltage to said first contact electrode and a second voltage to said second contact electrode.
 19. The method of claim 18, further comprising: varying said voltage difference between said first contact electrode and said second contact electrode to vary said capacitance of said chamber component.
 20. The method of claim 17, further comprising: varying a capacitance of said chamber component to increase a lifetime of said chamber component, improve matching between a first plasma processing chamber and a second plasma processing chamber, or compensate for a drift in said plasma-assisted process from one substrate to another substrate, or any combination of two or more thereof. 